在可攜式裝置的晶片中，通常需要動態電壓調變及快速儲存之特色以完成低功耗及穩定的關機程序。許多可攜式裝置的系統使用一個靜態隨機存取式記憶體以達成快速且低電壓之讀寫操作，並另外使用一個內嵌式快閃記憶體做為資料備份。然而，因序列式資料傳輸，使用二個記憶體的方式會造成資料轉輸時間過長。非揮發性靜態隨機存取式記憶體以平行方式傳輸資料，使得資料備份及資料復元時間更短，對可攜式裝置而言是個更好的選擇。
此作品為第一個已驗證之電阻式非揮發性靜態隨機存取記憶體(Rnv8T)，其架構由八個電晶體及二個電阻式記憶體元件所組成，可達到快速且低耗能非揮發性儲存動作和低讀寫操作電壓。
此Rnv8T cell 使用可快速儲存且低儲存電流之RRAM元件，三維堆疊於8T cell上方，使其達到低操作耗能與小的cell面積。另外，比傳統SRAM六個電晶體架構多出的二個電晶體，除了作為RRAM開關外還可提供靜態隨機存取式記憶體寫入輔助的功能。由於此寫入輔助功能，我們可調整電晶體大小以防止因元件製程漂移及雜訊影響，在低電壓下讀取失敗的情況。此16千位元Rnv8T晶片已下線驗證其讀寫及儲存/喚回功能，且最低讀寫操作電壓為0.45伏特，在所有非揮發性靜態隨機存取式記憶體與二個記憶體方式中，其儲存耗能及最低讀寫操作電壓最低。

Dynamic voltage scaling (DVS) and fast storage are required for mobile chips to achieve low-power and reliable power-off procedures. Many DVS mobile chips use SRAM for fast/low-VDDmin access and embedded Flash for data-backup. However, the 2-macro approach requires long store time due to serial data transfer. The nonvola-tile-SRAM (nvSRAM) provides a better solution for mobile chips, thanks to theirs fast bit-to-bit parallel data storage.
This work demonstrates the first fabricated macro-level RRAM-based nonvolatile SRAM (nvSRAM) that use a new 8T2R (Rnv8T) cell to achieve fast and low-energy NVM storage and low VDDmin read/write operations.
The Rnv8T cell uses two fast-write low-current RRAM devices, 3D stacked over the 8T, to achieve low store energy with a compact cell area (1.6x that of a 6T cell). A 2T RRAM-switch provides both RRAM control and write-assist functions. This write assist feature enables Rnv8T cell to use read favored transistor sizing against read/write failure at a lower VDD. The fabricated 16Kb Rnv8T macro achieves the lowest store energy and R/W VDDmin (0.45V) than other nvSRAM and “SRAM+NVM” solutions.

Abstract (Chinese) i
Abstract (English) ii
Acknowledgements (Chinese) iii
Content iv
List of Figures vii
List of Tables xi
Chapter 1 Introduction 1
1.1 Memories in SoC 1
1.2 Two-Macro Memory Solution 3
1.3 Nonvolatile SRAM 4
1.4 Thesis Organization 8
Chapter 2 Design Targets 10
2.1 Low Operation Voltage 10
2.1.1 Write Margin (WM) of 6T SRAM 11
2.1.2 Read Static Noise Margin (RSNM) of 6T SRAM 13
2.1.3 Bottleneck of VDDmin 16
2.2 Nonvolatile Memory Device Selection 17
2.3 Leakage Current Elimination 21
Chapter 3 Proposed Rnv8T SRAM Cell Scheme 23
3.1 Resistive Device [31] 23
3.1.1 Device Structure 24
3.1.2 Switching Mechanism 24
3.1.3 1T1R RRAM configuration 25
3.1.4 Comparison of different RRAM devices 26
3.2 Proposed Rnv8T Cell Structure 27
3.3 Proposed Cell Operation 28
3.3.1 Normal (SRAM) Operation 29
3.3.2 Store Operation 30
3.3.3 Restore Operation 31
3.4 Cell Analysis 32
3.4.1 Improvement of Write Speed 32
3.4.2 Improvement of Write Margin (WM) 34
3.4.3 Read Favored Sizing (RFS) 36
3.4.4 VDDmin Reduction 37
3.4.5 Restore Yield 38
3.4.6 Reliability 39
Chapter 4 Performance and Comparisons 41
4.1 Read/Write Performance 41
4.1.1 Write time 42
4.1.2 Write margin (WM) 42
4.1.3 Read Static Noise Margin (RSNM) 43
4.1.4 Minimal Supply Voltage (VDDmin) 44
4.2 Store/Restore Performance 45
4.2.1 Store time and energy consumption 45
4.2.2 Restore time 46
Chapter 5 Implementation 48
5.1 Cell layout 48
5.2 Macro structure 49
5.2.1 Divided Wordline Scheme 50
5.2.2 Timing Control of Replica Bitline Scheme 51
5.2.3 Test Modes 52
5.3 Macro Performance 53
Chapter 6 Experimental Result 55
6.1 Read/Write Operation 56
6.2 STORE/RESTORE Verification 56
6.3 Shmoo Plot 58
Chapter 7 Conclusion 59
7.1 Summary 59
7.2 Future work 61
Reference 63

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