帳號:guest(3.238.12.0)          離開系統
字體大小: 字級放大   字級縮小   預設字形  

詳目顯示

以作者查詢圖書館館藏以作者查詢臺灣博碩士論文系統以作者查詢全國書目
作者(中文):馮冠中
作者(外文):Feng, Kuan-Chung
論文名稱(中文):Floorplanning, TSV Assignment and Pin Assignment for 3D-IC Designs
指導教授(中文):麥偉基
指導教授(外文):Mak, Wai-Kei
學位類別:碩士
校院名稱:國立清華大學
系所名稱:資訊工程學系
學號:9762634
出版年(民國):99
畢業學年度:98
語文別:英文
論文頁數:40
中文關鍵詞:平面規劃直通矽晶穿孔腳位
外文關鍵詞:FloorplanningThrough-Silicon-ViaPin
相關次數:
  • 推薦推薦:0
  • 點閱點閱:118
  • 評分評分:*****
  • 下載下載:4
  • 收藏收藏:0
As technology advances, 3D-ICs are introduced for alleviating the interconnect scaling problem coming with shrinking feature size and increasing integration density. In 3D-ICs, one of the key challenges is the vertical Through-Silicon-Vias (TSVs) used for different device layers connection. In this thesis, we present a 3D-ICs fixed-outline floorplanner with TSV assignment and pin assignment. To find a good slicing floorplan, we generalize the notion of slicing tree based on the principle of Deferred Decision Making (DDM). Because of DDM, one slicing tree actually corresponds to a huge number of slicing floorplan solutions. We also consider the exact position of TSVs, which is never addressed in the previous works. Several techniques are also proposed to further optimize the total wirelength, such as whitespace re-distribution, non-boundary pin assignment. Experimental results show that our approach is efficient and effective for wirelength optimization and fast runtime.
由於製程越做越小導致晶片上之連線問題複雜化,三維立體積體電路視為一種可以消除連線問題複雜化的方法。然而,直通矽晶穿孔用來連接不同層的技術在三維立體積體電路設計下是設計的問題之一。這篇論文主要探討在三維立體積體電路設計下之平面規劃、分派直通矽晶穿孔及分派腳位之方法。首先,為了找到一個好的平面規劃,我們利用一種延後決定最後平面規劃結果的方法來產生一個不錯的解。接著透過重新規劃可用空間的方法讓直通矽晶穿孔能放在不錯的位置上。另外值得一提的是直通矽晶穿孔的位置是絕對位置;也就是說,我們準確地找到直通矽晶穿孔在該平面規劃下的座標。最後,考慮腳位在三維立體積體電路下的位置。不同於傳統的考量,我們將考慮腳位可以放置在每一個區塊範圍內的任意位置上。透過實驗結果得知,我們除了有效找到直通矽晶穿孔的絕對位置之外,不同於傳統的分派腳位位置,我們能夠獲得更好的總線長;同時,我們的方法也透過有效的整合,讓執行時間能在短時間內完成。
Acknowlegement
Abstract
Introduction
Preliminaries
Problem Definition
Algorithm
Experiment
Conclusion
Appendix A
[1]D. H. Kin, S. Mukhopaddhyay, and S. K. Lim. Through-Silicon-Via
Aware Interconnect Prediction and Optimization for 3D Stacked ICs.
In Proc. Workshop on System Level Interconnect Prediction,
2009.

[2]C. T. Lin, D. M. Kwai, Y. F Chou, T S. Chen, and W. C Wu. CAD
Reference Flow for 3D Via-Last Integrated Circuits. In Proc.
Asia and South Pacific Design Automation Conference, pages 187-192,
2010.

[3]Anne-Marie Corley. Design Challenges Loom for 3-D Chips. In Proc. International Solid-State Circuits Conference, 2010

[4]J. Cong, G. Luo, J. Wei, and Y. Zhang. Thermal-Aware 3D IC Placement
Via Transformation. In Proc. Asia and South Pacific Design
Automation Conference, 2007.

[5]B. Goplen and S. Sapatnekar. Placement of 3D ICs with Thermal and
Interlayer Via Considerations. In Proc. IEEE Int. Interconnect
Technology Conference, 2007.

[6]A. B. Kahng. Classical floorplanning harmful, In Proc.
International Symposium on Physical Design, pages 207-213, 2000.

[7]X. He, S. Dong, X. Hong, S. Goto. Integrated Interlayer Via Planning
and Pin Assignment for 3D ICs. In Proc. International Workshop
on System Level Interconnect Prediction, pages 99-104, 2009.

[8]X. He, S. Dong, et. al, Simultaneous Buffer and Interlayer Via
Planning for 3D Floorplanning. In Proc. International Symposium
on Quality Electronic Design, pages 740-745, 2009.

[9]J. Z. Yan, C. Chu. DeFer: deferred decision making enabled
fixed-outline floorplanner. In Proc. Design Automation
Conference, pages 161-166, 2008.

[10]G. Karypis and V. Kumar. Mutilevel K-way Hypergraph Partitioning. In Proc. Design Automation Conference, pages 343-348, 1999.

[11]T.-C. Chen, Y,-W. Chang, and S.-C. Lin. IMF: Interconnect-driven
multilevel floorplanning for large-scale building-module designs. In Proc. International Conference on Computer Aided Design, pages
159-164, 2005.

[12]S. Chen and T. Yosihmura. A Stable Fixed-Outline Floorplanning
Method. In Proc. International Symposium on Physical Design,
pages 119-127, 2007.

[13]J. Cong, M. Romesis and J. R. Shinnerl. Fast Floorplanning by
Look-Ahead Enabled Recursive Bipartitioning. In proc. Asia and
South Pacific Design Automation Conference, pages 1119-1122, 2005.

[14]R. K. Ahuja, T. L. Magnanti, and J. B. Orlin. Network Flows: Theory,
Algorithms, and Applications, Prentice Hall/Pearson, 2005.

[15]A. V. Goldberg. An efficient implememtation of a scaling
minimum-cost flow algorithm. Journal of Algorithm, 22(1):1-29, 1997.

[16]L. E. Liu and C. Sechen. Multilayer pin assignment for macro cell
circuits. In Proc. IEEE Trans. Computer-Aided Design, pages
1452-1461, 1999.

[17]X. Yao, M. Yamada, and C. L. Liu. A new approach to the pin
assignment problem. In Proc. Design Automation Conference,
pages 566-572, 1988.

[18]X. He, S. Dong. Pin Assignment for Wire Length Minimization after
Floorplanning Phase. In Proc. International Conference on
ASIC, pages 1294-1297, 2009.

[19]GSRC floorplan benchmarks.
http://vlsicad.eecs.umich.edu/BK/GSRCbench/.
 
 
 
 
第一頁 上一頁 下一頁 最後一頁 top
* *