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作者(中文):彭建濂
作者(外文):Peng, Chien-Lien
論文名稱(中文):適用於G.hn規範的使用排程演算法所實現之高吞吐量多模態低密度奇偶檢查碼解碼器
論文名稱(外文):A scheduling Algorithm for Higher-throughput Efficient Multi-mode G.hn LDPC decoder
指導教授(中文):翁詠祿
指導教授(外文):Ueng, Yeong-Luh
學位類別:碩士
校院名稱:國立清華大學
系所名稱:電機工程學系
學號:9761618
出版年(民國):99
畢業學年度:98
語文別:英文
論文頁數:29
中文關鍵詞:通道編碼低密度奇偶檢查碼解碼器
外文關鍵詞:channel codingLDPCdecoder
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低密度奇偶檢查(Low-density parity-check, LDPC) 碼為一具有強大改錯能力
的錯誤更正碼。近年來在多種通訊傳訊應用中, 當檢查節點(check node) 連結到變
量節點(variable node) 的個數較多時, 要實現一個高吞吐量且有效率的多模態低密
度奇偶檢查(LDPC) 解碼器仍然是個挑戰。在這篇論文中, 我們提出一種排程演算
法, 可將類循環低密度奇偶檢查(QC-LDPC) 碼的解碼運算切割成多個較小的運算
集合。排程演算法以欄位為基礎重新排序奇偶檢查矩陣(PCM) 的執行順序, 縮短
電路中最長路徑所需的抵達時間, 如此一來不但可以增加運算單元的使用率, 還可
以加快電路的操作頻率, 進而增加解碼吞吐量。基於此種以欄位為基礎的高吞吐量
多模態解碼器, 由於不同模態之間的切換存在著高複雜度的電路需要克服, 對此我
們利用類循環的特殊結構使得較複雜的繞線網絡可被簡單的多工器所取代, 在控制
電路方面也僅需要計數器加以控制即可。另外, 對於檢查節點運算值的儲存方式, 可
以使用記憶體以降低核心面積。使用這些技術, 我們可以完成一高吞吐量且支援多種
不同規範類循環低密度奇偶檢查碼解碼運算的多模態解碼器。綜合以上的方法, 我
們設計了一個適用於G.hn 規範的類循環低密度奇偶檢查碼解碼器電路。此電路晶
片在UMC 90奈米製程實現下, 核心面積為7.31 mm2, 且在操作頻率為400 MHz
時最高可到達到1.95Gb/s 的解碼吞吐量。
1 INTRODUCTION 1
1.1 Motivation . . . . . . . . . . . . . . . . . . 1
1.2 Thesis Organization . . . . . . . . . . . . . . . . . . . .2
2 LDPC CODES AND DECODING ALGORITHM 4
2.1 Parity-check matrix for QC-LDPC codes . . . . . . . . . . . . . 4
2.2 QC-LDPC codes in G.hn . . . . . . . . . . . . . . . . . . . . . . 4
2.3 Two phase message passing decoding . . . . . . . . . . . . . . . 6
3 DECODING SCHEDULE FOR QC-LDPC CODES 8
3.1 Column scheduling concept . . . . . . . . . . . . . . . . . . . . 8
3.2 Algorithm for column scheduling . . . . . . . . . . . . . . . . . 12
4 A HIGHER-THROUGHPUT EFFICIENT MULTI-MODE DECODER
FOR G.HN 15
4.1 Parameters related to CSA . . . . . . . . . . . . . . . . . . . . . 15
4.2 CNU and quasi-cyclic structure . . . . . . . . . . . . . . . . . . 16
4.3 Variable node unit (VNU) and pipeline processing . . . . . . . . 17
4.4 Multi-mode functionality . . . . . . . . . . . . . . . . . . . . . . 18
4.5 Implementation results . . . . . . . . . . . . . . . . . . . . . . . 19
4.6 Comparison with other works . . . . . . . . . . . . . . . . . . . 20
5 CONCLUSION 24
[1] R. G. Gallager, “Low density parity check codes,” IRE Trans. Inform.
Theory, vol. IT-8, pp. 21-28, Jan. 1962.
[2] D.-J.-C. MacKay, “Good error-correcting codes based on very sparse
matrices,” IEEE Trans. Inf. Theory, vol. 45, no. 2, pp. 399-431, March
1999.
[3] ITU-T G.hn standard for wired home networking. [On-line]. Available:
http://www.homegridforum.org/home/
[4] Digital video broadcasting (dvb); second generation. In ETSI EN 302
307 v1.1.1, 2005.
[5] IEEE p1901 - IEEE draft standard for standard for broadband over
power line networks: Medium access control and physical layer specifications.
[6] IEEE 802.16e WiMAX standard, IEEE P802.16e-2005, Oct. 2005.
[7] IEEE 802.11 Wireless LANs WWiSE Proposal: High throughput extension
to the 802.11 standard. IEEE 11-04-0886-00-000n
[8] R. Tanner, “A recursive approach to low complexity codes,” IEEE Trans.
Inform. Theory, vol. 27, no. 5, pp. 533-547, Sept. 1981.
[9] A.-J. Blanksby and C.-J. Howland, “A 690-mW 1-Gb/s 1024-b, rate-1/2
low-density parity-check code decoder,” IEEE J. Solid-State Circuits,
vol. 37, no. 3, pp. 404-412, March 2002.
[10] T. Brack, M. Alles, F. Kienle, and N. When, “A synthesizable IP core for
WiMAX 802.16e LDPC code decoding,” in Proc. IEEE 17th Int. Symp
Pers., Indoor, Mobile Radio Commun., Sep. 2006, pp. 1-5.
[11] Y.-L. Ueng, C.-J. Yang, K.-C. Wang and C.-J. Chen, “A multi-mode
shuffled iterative decoder architecture for high-rate RS-LDPC codes,” to
apear in IEEE Trans. Circuits Syst. I, Reg. Papers.
[12] G. Gentile, M. Rovini, and L. Fanucci, “Low-complexity architectures of
a decoder for IEEE 802.16e LDPC codes,” in Proc. Euromicro Conf. on
Digital System Design Architectures, Methods and Tools (DSD), pp. 369-
375, Aug. 2007.
[13] C. -H. Liu, C. -C. Lin, S. -W. Yen, C. -L. Chen, H. -C. Chang, C. -Y. Lee,
Y. -S. Hsu and S. -J. Jou, “Design of a multimode QC-LDPC decoder
based on shift-rounting network,” IEEE Trans. Circuits Syst. II, Express
Briefs, vol. 56, no. 9, pp. 684-394, Sep. 2009.
[14] C.-H. Liu, S.-W. Yen, C.-L. Chen, H.-C. Chang, C.-Y. Lee, Y.-S. Hsu,
and S.-J. Jou, “An LDPC decoder chip based on self-routing network for
IEEE 802.16e applications,” IEEE J. Solid-State Circuits, vol. 43, no. 3,
pp. 684-694, March 2008.
[15] J. Zhang, and M. P. C. Fossorier, “Shuffled iterative decoding,” IEEE
Trans. Commun., vol. 53, no. 2, pp. 209-213, Feb. 2005.
[16] M. Karkooti, P. Radosavljevic, and J. R. Cavllaro, “Configurable, high
throughput, irregular LDPC decoder architecture: Tradeoff analysis and
implementation,” in Proc. IEEE Appl.-Specific Syst., Archit. Process.,
Sep. 2006, pp. 360-367.
[17] K. Zhang, X. Huang, Z. Wang, “High-throughput layered decoder implementation
for quasi-cyclic LDPC codes,”IEEE J. Selected Area in
Comm., vol. 27, no. 6, pp. 985-994, Aug. 2009.
[18] J. Chen and M.-P.-C. Fossorier, “Density evolution for two improved
BP-based decoding algorithms of LDPC codes,” IEEE Commum. Lett.,
vol. 6, pp. 208-210, May 2002.
[19] Y. Chen and K. K. Parhi, “Overlapped message passing for quasi-cyclic
low-density parity check codes,” IEEE Trans. Circuit Syst. I, Reg. Papers,
vol. 51, no. 6, pp. 1106-1113, Jun. 2004.
[20] L. Liu and C.-J. Richard Shi, “Sliced message passing: high throughput
overlapped decoding of high-rate low-density parity-check codes,” IEEE
Trans. Circuits Syst. I, Reg. Papers, vol. 55, no. 11, pp. 3697-3710, Dec.
2008.
[21] J. Sha, J. Lin, Z. Wang, L. Li and M. Gao, “Decoder design for RS-based
LDPC codes,” IEEE Trans. Circuits. Syst. II, Exp. Briefs, vol. 56, no.
9, pp. 724-728, Sep. 2009.
[22] J. Sha, Z. Wang, M. Gao, and L. Li, “Multi-Gb/s LDPC code design
and implementation,” IEEE Trans. VLSI, vol. 17, no. 2, pp. 262-268,
Feb. 2009.
[23] “G.hn: Improved LDPC matrices for G.h”, DS2, Valencia, Spain 16-20
Nov. 2009.
[24] D.-E. Hocevar, “A reduced complexity decoder architecture via layered
decoding of LDPC codes,” in Proc. IEEE Workshop on Signal Processing
Systems (SIPS), pp. 107-112, Oct. 2004.
[25] G. Masera, F. Quaglio, and F. Vacca, “Implementation of a flexible
LDPC decoder,” IEEE Trans. Circuits. Syst. II, Exp. Briefs, vol. 54, no.
6, pp. 542-546, June 2007.
[26] M. M. Mansour and N. R. Shanbhag, “A 640-Mb/s 2048-bit programmable
LDPC decoder chip,” IEEE J. Solid-State Circuits, vol. 41,
no. 3, pp. 684-698, Mar. 2006.
[27] T. Brack, M. Alles, T. Lehnigk-Emden, F. Kienle, N. Wehn, N.-E.
L’Insalata, F. Rossi, M. Rovini, and L. Fanucci, “Low complexity LDPC
code decoders for next generation standards,” in Proc. Design, Automation
and Test in Europe Conf. and Exhibition, pp. 16-20, April 2007.
[28] X. -Y. Shih, C. -Z. Zhan, C. -H. Lin, and A. -Y. Wu, “An 8.29mm2
52mW multi-mode LDPC decoder design for mobile WiMAX system in
0.13μm cmos process,” IEEE J. Solid-State Circuits, vol. 43, no. 3, pp.
672-683, Mar. 2008.
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