在這篇論文裡面，我們提出了一個具有寬廣的頻率追蹤範圍的標準單元化(standard cell-based)全數位鎖相迴路(All-Digital Phase-Locked Loop, ADPLL)。除此之外，我們也提出了一個結合三種不同的控制方法(包含延遲路徑選擇、控制驅動能力以及控制負載電容)及使用新的排列方式組合而成的三段調控式數位控制震盪器(Three-Gear Digitally Controlled Oscillator, 3G-DCO)，可同時達到改善數位控制震盪器可提供之最高頻率、頻率範圍及解析度的目的。搭配我們所提出的鏡像式數位控制震盪器的校準機制(Mirror-DCO-Based Calibration Mechanism)以及智慧型控制碼跳躍機制(Smart Code-Jumping Mechanism)，當三段調控式數位控制震盪器所產生的週期來到某一個週期區間的端點時，它可以直接跳至鄰近的週期區間中，週期與當下的週期最相近的點。如此一來，我們的ADPLL可以克服先前數位控制震盪器所面臨的非連續性的問題，創造出一個幾乎連續的頻率追蹤範圍，讓ADPLL更適合操作在擁有溫度變異的環境中，並且能更接近傳統類比電路的效能。另外，在設計此ADPLL的過程中，我們採用了一般標準單元電路設計的設計流程，更縮短了其電路在更換製程時所耗費的時間。我們利用TSMC 0.18□m 之標準單元庫來實現此電路，經過佈局後之實驗結果顯示，我們所提出的三段調控式數位控制震盪器在TT-corner的情況下，可以操作在89 MHz ~ 1013 MHz 並且具有 2.54 ps 的平均解析度。而當ADPLL鎖定在1000 MHz 時，其方均根時脈抖動量及峰對峰的時脈抖動量分別為2.2 ps 與 17 ps。

A fully standard cell-based all-digital phase-locked loop (ADPLL) with wide tracking range of frequency is presented. The three-gear digitally controlled oscillator (3G-DCO) designed in this work adopts three different control methods (including path-selection, driving-strength controlling, and loading capacitance controlling) and a novel configuration to achieve the goal of improving not only the maximum output frequency, but also the output frequency range and the resolution of the DCO simultaneously. Combined with a proposed Mirror-DCO-Based Calibration Mechanism and a Smart Code-Jumping Mechanism, when the 3G-DCO arrives at the end-point of one clock-period region, it can immediately jump to the point in the adjacent clock-period region which has the closest clock period to the current one. In this way, we can overcome the discontinuity problem faced by most previous DCO’s to create an almost continuous frequency tracking range similar to an analog DCO, and make the ADPLL suitable for operations with temperature variation. Besides, the proposed ADPLL can be designed by following the general cell-based design flow, so that, it can decrease the design cycle time in a new process. Using TSMC 0.18□m CMOS technology, the simulation result shows that the three-gear digitally controlled oscillator designed in this work can operate from 89 MHz to 1013 MHz with 2.54 ps of average resolution (at TT-corner), and the proposed ADPLL has the RMS and the peak-to-peak jitter of 2.2 ps and 17 ps at 1000 MHz, respectively.

Abstract i
摘要 ii
致謝 iii
Content iv
List of Figures vi
List of Tables vii
Chapter 1 Introduction 1
1.1 Introduction 1
1.2 Thesis Organization 2
Chapter 2 Preliminaries 3
Chapter 3 Circuit Architecture 6
3.1 Overall Architecture 6
3.2 Three-Gear Digitally Controlled Oscillator 8
3.2.1 Alpha-Part 9
3.2.2 Beta-Part 9
3.2.3 Gamma-Part 9
3.3 Locking Procedure 13
3.3.1 □-code Detection 13
3.3.2 Mirror-DCO-Based Calibration 14
3.3.3 Frequency Detection 14
3.3.4 Preliminary Phase Locking 15
3.3.5 Jitter Minimization 15
Chapter 4 Tracking Algorithm with Smart Code-Jumping Mechanism 16
4.1 Mirror-DCO-Based Calibration Mechanism 17
4.1.1 Operation Procedure 18
4.1.2 Architecture of the Frequency Comparator 19
4.2 Smart Code-Jumping Mechanism 21
Chapter 5 Experimental Results 22
5.1 Post-Layout Simulation Results 22
Chapter 6 Conclusion 28
Bibliography 29

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