時間至數位轉換器(Time-to-digital converter, TDC)迄今在各個領域都有廣泛的應用，其中包含雷射測距儀(Time-of-flight laser range finder)、超音波厚度測量(Ultrasonic thickness measurement)、高能粒子探測器(High energy physics particle detector) 、晶片抖動測量(On-chip jitter measurement)、射頻全數位頻率合成器(RF all-digital frequency synthesizer)等等。各種應用皆有不同的時差解析度(timing resolution)以及動態範圍(dynamic resolution)的要求。

本篇論文中，高時差解析度、大動態範圍、低功率消耗的時間至數位轉換器在此提出。傳統中以延遲線為基礎的時間至數位轉換器的解析度受限於製程的閘延遲。近年來，游標尺式(Vernier delay line)、內插式(Time interpolation)、時間放大(Time residue amplification)等技巧已被提出用來打破時間至數位轉換器在解析度的限制。然而，因為提高解析度伴隨而來的是面積及功率消耗的急
遽增加。

此時間至數位轉換器以計數器重複使用內部的延遲細胞(Delay-cell)，搭配多路徑環形振盪器(Multipath ring oscillator)提高解析度。藉由雙計數器與狀態至相位邏輯(State-to-phase logic)達到準確的時間轉換。由於影響多路徑環形振盪器其震盪頻率的因素眾多，為了節省設計的時間與複雜度，此多路徑環
形振盪器藉著改善後的時間與功率模型分析做最佳化的處理。晶片的製作採用台積電90-nm 1P9M 製程來實現，晶片面積為0.18mm2，在1.2-V 的工作電壓下其時間至數位轉換器的解析度小於6ps，功率消耗則為9.6mW。

This thesis reports the design and implementation of a time-to-digital convertor (TDC) with high resolution, wide detect range, and low power dissipation. Conventionally, the time resolution of a conventional delay-line based TDC is usually limited by the delay cell. Recently, several TDC structures have been proposed to provide sub-gate-delay resolutions, such as Vernier delay line, passive time interpolation, and time residue amplification. However, the finer resolution makes the number of delay elements grow fast.
This work describes a counter-based high-resolution TDC with a multi-path ring oscillator (MRO) as the timing generator. Precise conversion of sub-gate-delay resolution is based on a pair of counters and state-to-phase (S2P) logics. The MRO is optimized with an improved timing model and power consumption analysis. Running from a single 1.2-V power supply, experimental results for the TDC prototype show that less than 6 ps resolution is achieved with 9.6mW power consumption. The TDC has been fabricated in a tandard 90-nm CMOS process. The die area is 0.18 mm2.

1 Introduction 1
1.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Thesis Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2 Background on Time-to-Digital Converter 3
2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.2 Analog Time-to-Digital Converter . . . . . . . . . . . . . . . . . . . . . . . . 5
2.2.1 Time-to-Voltage TDC . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.2.2 Dual Slope Integration . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.3 TDC with Gate-Delay Resolution . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3.1 Scaling Theory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3.2 Classical Delay-Chain TDC . . . . . . . . . . . . . . . . . . . . . . . 9
2.3.3 Cyclic Delay-Chain TDC . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.4 TDC with Sub-Gate-Delay Resolution . . . . . . . . . . . . . . . . . . . . . . 12
2.4.1 Pulse Shrinking Delay Element . . . . . . . . . . . . . . . . . . . . . 12
2.4.2 Vernier Delay Line (VDL) TDC . . . . . . . . . . . . . . . . . . . . . 13
2.4.3 Delay Interpolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
ii
CONTENTS
2.4.4 Oscillator-Based TDC . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3 Multipath Ring Oscillator Design 21
3.1 Achieving Sub-Gate-Delay Row Resolution . . . . . . . . . . . . . . . . . . . 22
3.2 Multi-Inputs Delay Element Implementation . . . . . . . . . . . . . . . . . . . 25
3.3 Delay Time Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.3.1 Single-Path Ring Oscillator . . . . . . . . . . . . . . . . . . . . . . . 25
3.3.2 Multipath Ring Oscillator . . . . . . . . . . . . . . . . . . . . . . . . 27
3.4 Power Consumption Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.4.1 Major Sources of Power Consumption . . . . . . . . . . . . . . . . . . 34
3.4.2 Power Consumption of Multi-Input Delay Element . . . . . . . . . . . 35
3.5 Layout Complexity Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.6 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
4 Hardware Efficient MRO TDC in An All-Digital Frequency Synthesizer Applica-
tion 41
4.1 Phase-Domain All-Digital Frequency Synthesizer . . . . . . . . . . . . . . . . 42
4.2 The Proposed Circuit Architecture . . . . . . . . . . . . . . . . . . . . . . . . 44
4.3 Multiphase Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
4.3.1 Design Consideration of the MRO . . . . . . . . . . . . . . . . . . . . 48
4.4 Fractional Phase Read-Out Circuit . . . . . . . . . . . . . . . . . . . . . . . . 51
4.4.1 Measurement Entirely with Counters . . . . . . . . . . . . . . . . . . 51
4.4.2 Measuring Frequency by Tracking Phase . . . . . . . . . . . . . . . . 52
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CONTENTS
4.4.3 State-to-Phase (S2P) Logic . . . . . . . . . . . . . . . . . . . . . . . . 54
4.5 Integer Phase Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
4.6 Phase Combiner . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
5 Chip Implementation and Measurement Result 62
5.1 Chip Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
5.2 Measurement Setup and Experimental Result . . . . . . . . . . . . . . . . . . 64
5.2.1 On-Chip Measurement Unit . . . . . . . . . . . . . . . . . . . . . . . 68
5.2.2 TDC Characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
5.2.3 INL/DNL characteristic . . . . . . . . . . . . . . . . . . . . . . . . . 71
5.2.4 TDC Code Distribution . . . . . . . . . . . . . . . . . . . . . . . . . . 71
5.3 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
6 Conclusion and FutureWork 76
6.1 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
6.2 Future work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Appendix A vi

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